In communication system, either wideband or narrowband receiver often operate with signals well below full scale. And it is required that the analog-to-digital converter feature good Spurious Free Dynamic Range (SFDR).
As to high-speed high-resolution analog-to-digital converters (ADCs), SFDR is determined by two factors: 1. the distortion of the front-end amplifier and sample-and-hold circuit; 2. the distortion brought by non-linearity of transfer function of ADC, namely, differential nonlinearity (DNL). When input signal features small amplitude, the front-end amplifier and sample/hold circuit feature good linearity, so the distortion brought by front-end amplifier and sample/hold circuit can be ignored. However, even insignificant non-linearity of ADC's transfer function cause harmonics. Particularly, when input signal amplitude and quantization step feature the same order of magnitude, the distortion can be serious in ways that decrease SFDR. Therefore, when input signal features small amplitude, DNL error must be reduced to increase ADC's SFDR.
At present, a noise dither technique to decrease DNL error of ADC and improve SFDR is shown in FIG. 1: The analog-to-digital converter system is taken as a “Black box”. A pseudorandom sequence signal, as a dither signal, goes through the digital-to-analog converter (DAC) and comes out as an analog dither signal. The analog dither signal is added to the analog input signal, then being quantized by ADC system. The dither signal is eliminated by digital subtracter in the digital domain before the output of final digital code.
Technically, it is very difficult to effectively remove dither signals, because the analog dither signal being injected to analog front-end, is required to equal to the dither signal being eliminated in the digital domain. Otherwise, the output of final digital code consists of tremendous information about dither signals which increases noise floor of ADC. It is clear that higher resolution is required for DAC in such situation, and the digital-to-analog converter is required to have the same quantization bits as ADC. In the other word, a DAC is integrated into the ADC, featuring the same resolution of the ADC. The complexity of the ADC system increases as the quantization bits of the ADC increases. Therefore, this technology is limited for high-resolution analog-to-digital converters.